The present invention generally relates to a chain RAM (Random Access Memory) and a method for fabricating thereof. More particularly, the present invention relates to a chain RAM using ferroelectric capacitors or high-xcexa capacitors.
There has been a ferroelectric RAM (Random Access Memory) having a ferroelectric capacitor as a memory node or storing node. In a ferroelectric capacitor, electrolytic polarization is produced in crystal grains of a crystal structure oxide layer, included in a ferroelectric layer, when a voltage is applied to the capacitor. This voltage-electrolytic polarization characteristic has hysteresis. In a FeRAM, data of xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d are written and read using such hysteresis.
A conventional ferroelectric memory cell includes a FET (Field Effect Transistor) and a ferroelectric capacitor. The FET is connected at a gate to a word line WL. One of source and drain of the FET is connected to a bit line BL and at the other to an electrode of the ferroelectric capacitor. The ferroelectric capacitor is connected at the other electrode to a plate line PL.
A ferroelectric RAM (FRAM) has excellent characteristic of high speed read and write operations at a lower voltage. Such a FRAM includes a plurality of memory cell each having one transistor and one ferroelectric capacitor. The ferroelectric capacitor and transistor are connected in parallel, and the memory cells are connected in serial.
However, according to the above-described conventional chain FRAM, a voltage signal is applied to a selected memory cell through non-selected memory cells, therefore, voltage waveform at the electrodes of the ferroelectric capacitor for the selected memory cell is not stable. In other words, voltage waveform applied to the selected memory cell varies depending on its connected location in the FRAM. As a result, it is difficult to provide stable operation with the conventional chain FRAM.
Accordingly, an object of the present invention is to provide a chain FRAM having ferroelectric capacitors with symmetric characteristic so that the FRAM operates stably.
Another object of the present invention is to provide a ferroelectric capacitor with symmetric characteristic.
The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
Additional objects, advantages and novel features of the present invention will be set forth in part in the description that follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
According to a first aspect of the present invention, a chain ferroelectric RAM includes a memory cell array having a plurality of memory cells connected in series between a bit line and a plate line. Each memory cell includes a first ferroelectric capacitor having upper and lower electrodes between which a ferroelectric layer is provided; a second ferroelectric capacitor having upper and lower electrodes, between which a ferroelectric layer is provided; and a transistor connected to the upper and lower electrodes of the first and second ferroelectric capacitors. The upper electrode of the first ferroelectric capacitor is connected to the lower electrode of the second ferroelectric capacitor, and the lower electrode of the first ferroelectric capacitor is connected to the upper electrode of the second ferroelectric capacitor in a complimentary manner.
According to a second aspect of the present invention, a method includes the steps of providing a semiconductor substrate; providing an insulating layer on the semiconductor substrate; providing lower electrodes of first and second ferroelectric capacitors on the insulating layer; providing ferroelectric layers on the lower electrodes of the first and second ferroelectric capacitors; providing upper electrodes on the ferroelectric layers of the first and second ferroelectric capacitors; connecting the lower electrode of the first ferroelectric capacitor to the upper electrode of the second ferroelectric capacitor, and connecting the upper electrode of the first ferroelectric capacitor to the lower electrode of the second ferroelectric capacitor in a complimentary manner.